Home FAQs Example FAQs Here you will find an example set of FAQs. Filter     Order  Title asc Title desc Ordering    Display #  5 10 15 20 25 30 50 Item Title How to use ChipMason VEditor to extract connectivity information Dealing with incomplete netlists How to iterate across the module definitions and module items. Check for correct physical connectivity How assigns can be translated into a buffer of choice using the HwMapper How assigns can be translated into wires Flattening operation on a netlist Generating a report for a design using hierReport Performing a global rename operation Example of hierarchical write out options Read in same netlist in multiple designs Basic flattening operation on a netlist How to reduce the netlist size Using ecoEditor functions, to connect pins togheter. Using ecoEditor functions, to disconnect pins of the instance Debussifying an entire netlist How to create a stub for a verilog Using VEditor to extract connectivity information Using VEditor to report all counts and estimated cell area Reading in a library and a Verilog netlist How to use pdDisplay ? How to compare two designs with ncomp ? How to read in two different libraries and use the tool to compare the equivalent library cells. How to read in a library and use writeLiberty to save the library and add cells' name prefix How to read in a library, compile and save it How to convert library to verilog stubs? How to analyze a new library How do I download ChipMason What is "ChipMason"   << Start < Prev 1 Next > End >> Results 1 - 29 of 29 [ Back ]