 Our EDA products focus on the physical design of the chip in general and particularly on floorplanning, partitioning and hierarchical physical design with layout re-use. We provide our users with a design environment and an EDA flow where they can tackle very complex chips - many millions of instances - efficiently targeting deep sub micron technologies.
chipMason™ is a floorplanning and rapid silicon prototyping EDA toolset that supports hierarchical design flow and layout re-use methodology. It has a top level virtual router that supports top level routing with flexible repeater insertion and allocation. It has a fast built-in static timing analyzer (STA) allowing the user to perform time budgeting for their chip.
chipMason uses standard industry formats (LEF, DEF, LIB, SDC, Verilog), allowing its users to easily integrate it in their own ASIC EDA flows. ChipEDA can help its customers integrate and customize chipMason into their design flows. floorMason™ - Floorplanning and Silicon prototyping
floorMason is an integral part of chipMason. It is a hirarchical chip floor planner. It enables users tos partition large designs and create accurate layout and timing abstracts and budgets. They can go from logic design view to a detailed floorplan with IO pads, power grid, block placement and pin assignment allowing them to quickly find and fix routing congestions as well as critical timing paths. floorMason automates the block placement, pin placement and power grid generation.
Users start using our floorplanning tool at conceptual stage of their design, after the design is partitioned, each one of the hierarchical blocks is instrumented with repeater buffers. Virtual route is performed on the top level of the chip taking into account the routing congestion and the availability of repeater buffers.
vRAute™ - Virtual Router with Repeater Allocation
One of the unique features of chipMason tool set is re-use support. This capability is achieved through our technology vRAute™ It allows top level routing through the hierarchical blocks, utilizing repeaters already inserted in the blocks to buffer long nets, to optimize wire length.
Using this technology, the top level wires are shielded and therefore do not interfere with the block level wires. For more details on this feature, please see our paper Top-Down SoC Floorplanning with ReUse.
budgetMason™ - timing budgeting for hierarchical design
Based on the initial block placement, and the initial virtual route accurate top level wire delays are calculated and new accurate timing constaints for all the hierarchical blocks are generated. GENERATORS
ChipEDA provides several generators, built into chipMason tool set to help the user accelerate their design tasks. These generators can be used at different stages of the design phase to solve time consuming tasks like planning and designing the ioring and ensuring is it consistent with the package design.
dpMason™ - data path generator
Users of dpMason can generate very effecient data path structures based on the standard cell library. ChipEDA provides their customers with a complete flow to integrate the generated logic with their ASIC flow. We provide many built-in function as part of dpMason, the user can expand these functions or build new ones.
rfMason™ - register file and small memory generator
rfMason is a special application of dpMason, it is focused on generating special small memory arrays, like multi port register files or small fifos. An example of small memory arrays generated using rfMason are 6 read, 3 write 32x128 register file. Another examples are TAG RAMs, or CAM arrays.
ioMason™ - io ring generator
Users of ioMason™ use it to perform package/chip co-design giving them quick feedback on their package design and routability and top level chip floorplanning.
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